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Job Description:

Participate ASIC digital verification for various IP/SoC projects;

Create verification plans with designers;

Develop DV architecture and verification environment;

Conduct verification execution and sign-off.

Qualification:

Excellent team working style;

Solid IP/SoC verification background;

Mass production experience for verified IP/SoC;

Bachelor with 2+ years of working experience in ASIC digital verification;

Production experiences in verification strategies and test plans;

Familiar with System Verilog/UVM for test bench creation, debug, reuse, constrained-random stimulus and functional coverage;

Production experience in ARM buses, such as AXI/AMBA/APB is a plus;

Familiar with verification tools;

Familiar with Linux, Csh/Python or any script languages;

Good English skills (both read and write).


HR Contact:

Job Description:

Write micro-architecture definition/IC design spec;

Write RTL coding for block or top level;

Do IP level synthesis/timing analysis/formality check/CDC check/Code coverage check;

Assist verification engineer to complete module and top level simulation and verification;

Debug RTL/Gate Level waveform at module or top level;

Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.

Qualification:

MSEE with 2+ years of experience in digital design;

Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;

Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys VCS, DC, PT, etc.;

Basic skills of Script and be familiar with TCL, Perl, etc.;

Self-motivated, good team work spirit and good communication skills;

At least 3+ years of experience in one of the following field:

Experience in CPU/GPU/DSP/image processing design;Experience in AXI/AHB/APB protocols and ARM-based fabric design;Experience in DDR controller design or integration of DDR controller and PHY in large SoC;Experience in PCIe controller design or integration of PCIe controller and PHY in large SoC;Experience in using System Verilog, UVM to do verification.
HR Contact:

Job Description:

Work with technical marketing to define SoC product for CPU/AI/computer system;

Write the SoC architecture and requirement specs;

Do high level modeling and simulations;

Work with project lead to conduct feasibility analysis, define design strategy and planning;

Keep up to date with latest SoC for CPU/AI/computer system.

Qualification:

Master or Ph.D degree with 5+ years of experience in SoC architecture design;

Proven track record of SoC architecture definition and product design;

Familiar with RISC architecture, on chip bus protocols, memory and coherency;

Familiar with SoC I/O interface controller/PHY such as DDR/PCIe/USB/AV interfaces;

Solid background in CPU architectures and operations with specialty in memory/cache control and management;

Familiar with System Verilog and/or System C;

Positive mindset, self-driven and good team player;

Excellent written and oral communication skills in both Chinese and English.


HR Contact:

Job Description:

Help IC architecture and micro-architecture design;

Responsible for specification and RTL coding for the given block;

Work with DV team to define the test plan and verify the RTL thoroughly;

Work with SoC team to guarantee successful integration;

Synthesize the design and provide timing constraints to the physical design team to ensure RTL meets timing.

Qualification:

Master or Ph.D degree with 10+ years of experience in SoC architecture design;

Proven track record of SoC architecture definition and product design;

Familiar with RISC architecture, on chip bus protocols, memory and coherency;

Familiar with SoC I/O interface controller/PHY such as DDR/PCIe/USB/AV interfaces;

Solid background in CPU architectures and operations with specialty in memory/cache control and management;

Familiar with System Verilog and/or System C;

Positive mindset, self-driven and good team player;

Excellent written and oral communication skills in both Chinese and English.


HR Contact:

Job Description:

Mainly responsible for Lab welding;

Manage lab instrument and components;

Manage Lab inventory;

Responsible for the cleanliness of the LAB.

Qualification:

Skilled in welding the PCB, especially SMT chips;

Skilled in using computer and lab instrument is preferred;

1+ years of related experience in laboratory or factory ;

Technical school diploma or college associate degree.


HR Contact:

Job Description:

ATE test program (software and hardware) production sustaining of Montage's memory buffer products and also Jintide?  CPU / HSDIMM? products, including initial test program production release, test program transfer among different suppliers, optimize and improve test program in mass production, help R&D improve DFT design, etc.

Qualification:

China Tier-1 University or above. Master/Ph.D preferred;

5+ years of experience in ATE test engineering in IC industry;

3+ years of experience in ATE test for ULSI (e.g. CPU, GPU, SOC, etc.);

Familiar with Advantest 93K Tester;

Skillful in writing and debugging test program;

Expertise in ATPG, BIST and other DFT technologies is preferred;

Experience in any kind of CPU (for Server, PC, Smartphone, and etc.) is preferred.


HR Contact:

Job Description:

Develop X86 performance analysis tool;

Do full system bottleneck analysis and performance tuning on X86 servers.

Qualification:

Master with 2+ years or bachelor with 3~5 years of experience in computer science or electronics;

Familiar with X86 architecture/ISA, knowledge of X86 micro-architecture is a plus;

Familiar with performance profiling tools, such as perf, PMC, Ftrace, etc.;

Familiar with Linux kernel subsystems or Windows system;

Experience in large-scale applications analysis and tuning is a big plus;

Self-motivated, good team work spirit and good communication skills.


HR Contact:

Job Description:

RD on algorithms related to computer vision and deep learning;

Support RTL implementation.

Qualification:

M.S. in Computer Science, Electrical, or Applied Mathematics;

2+ years of experience in computer vision, deep learning and optimization methods;

Familiar with basic algorithms on objective detection, recognition, tracking and etc.;

At least familiar with one deep learning framework;

Excellent programming expertise in Python, Matlab and C/C++ is required;

Self-motivated, good team work spirit and good communication skills.


HR Contact:

Job Description:

Participate in the AI accelerator architecture discussion and definition;

Write toolchain/compiler for the AI accelerator;

Help AE in generating numerous test cases for different applications using different neural networks;

Help doing and debugging of the hardware-software co-simulation issues related with compiler;

Support AI accelerator validation and debugging on the FPGA system and silicon;

Support AE in the usage and promoting of the SoC.

Qualification:

MSEE with 2+ years of experience in compiler design;

In depth knowledge of CPU/GPU/NPU/DSP architecture;

Strong knowledge of hardware-software co-design and knowing how to optimize the whole design to achieve high efficiency;

Strong programming skills and knowing how to optimize program to reach maximum performance under given hardware;

Self-motivated, good team work spirit and good communication skills.


HR Contact:

Job Description:

Develop Linux or Windows driver;

Develop test tools for chip.

Qualification:

Master with 2+ years or bachelor with 3~5 years of experience in computer science or electronics;

Familiar with developing Linux driver or Windows driver code is necessary;

Familiar with C language is necessary;

Knowledge of x86 System, I2C/SPI protocol, etc.;

Graphic UI development with Python QT or other tool is a plus;

Script language such as Python is a plus;

UEFI bios knowledge is a plus;

Linux kernel knowledge is a plus;

Good communication skill, team work spirit, self-motivated.


HR Contact:

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